1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an antenna ratio countermeasure circuit.
2. Description of the Background Art
Conventionally, it has been known that, when an antenna ratio exceeds a certain value in a CMOS LSI, a gate oxide film in an MOS transistor is damaged during a plasma process and a characteristic of the MOS transistor is deteriorated. Here, the antenna ratio refers to a ratio between a surface area of a metal interconnection, a via hole and the like that are electrically charged during the plasma process and an area of the gate oxide film connected thereto.
In order to address this problem, a first method, in which a layout of the metal interconnection, the MOS transistor and the like is devised so as to achieve the antenna ratio equal to or smaller than the prescribed value, and a second method, in which a diode is connected between the gate of the MOS transistor and a line of a power supply voltage or a ground voltage so as to release charges born by the gate, are available (see, for example, Japanese Patent Laying-Open No. 06-061440). According to the second method, even when the antenna ratio is infinite, the gate oxide film in the MOS transistor is not damaged.
Even if the second method is adopted, however, the gate oxide film in the MOS transistor is damaged during the plasma process, as the MOS transistor is reduced in size.
If both of the first method and the second method are adopted, damage to the gate oxide film can be prevented. In this case, however, the layout is restricted in order to achieve the antenna ratio not larger than the certain value, and the degree of freedom in process development is lowered due to necessity to consider plasma damage.